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<a href="#define-members">Macros</a>  </div>
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<div class="title">IFSR Bits<div class="ingroups"><a class="el" href="group__CMSIS__IFSR.html">Instruction Fault Status Register (IFSR)</a></div></div>  </div>
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<p>Bit position and mask macros.  
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:gafb3d593ec56834b6a265744efd6340a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#gafb3d593ec56834b6a265744efd6340a8">IFSR_ExT_Pos</a>&#160;&#160;&#160;12U</td></tr>
<tr class="memdesc:gafb3d593ec56834b6a265744efd6340a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: ExT Position.  <a href="#gafb3d593ec56834b6a265744efd6340a8">More...</a><br/></td></tr>
<tr class="separator:gafb3d593ec56834b6a265744efd6340a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab0083a1d82b370a7e5208e39267bda22"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#gab0083a1d82b370a7e5208e39267bda22">IFSR_ExT_Msk</a>&#160;&#160;&#160;(1UL &lt;&lt; IFSR_ExT_Pos)</td></tr>
<tr class="memdesc:gab0083a1d82b370a7e5208e39267bda22"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: ExT Mask.  <a href="#gab0083a1d82b370a7e5208e39267bda22">More...</a><br/></td></tr>
<tr class="separator:gab0083a1d82b370a7e5208e39267bda22"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadfd49185eeb102fc69e0a0d28fd2c4a4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#gadfd49185eeb102fc69e0a0d28fd2c4a4">IFSR_LPAE_Pos</a>&#160;&#160;&#160;9U</td></tr>
<tr class="memdesc:gadfd49185eeb102fc69e0a0d28fd2c4a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: LPAE Position.  <a href="#gadfd49185eeb102fc69e0a0d28fd2c4a4">More...</a><br/></td></tr>
<tr class="separator:gadfd49185eeb102fc69e0a0d28fd2c4a4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga20639ca32a866d7b021e455b7a5d24c6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#ga20639ca32a866d7b021e455b7a5d24c6">IFSR_LPAE_Msk</a>&#160;&#160;&#160;(0x1UL &lt;&lt; IFSR_LPAE_Pos)</td></tr>
<tr class="memdesc:ga20639ca32a866d7b021e455b7a5d24c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: LPAE Mask.  <a href="#ga20639ca32a866d7b021e455b7a5d24c6">More...</a><br/></td></tr>
<tr class="separator:ga20639ca32a866d7b021e455b7a5d24c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ecf4e123cfee3f0a19898a822fc0f62"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#ga9ecf4e123cfee3f0a19898a822fc0f62">IFSR_FS1_Pos</a>&#160;&#160;&#160;10U</td></tr>
<tr class="memdesc:ga9ecf4e123cfee3f0a19898a822fc0f62"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: FS1 Position.  <a href="#ga9ecf4e123cfee3f0a19898a822fc0f62">More...</a><br/></td></tr>
<tr class="separator:ga9ecf4e123cfee3f0a19898a822fc0f62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6fc93a02fbd1c968c70786a84428fca6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#ga6fc93a02fbd1c968c70786a84428fca6">IFSR_FS1_Msk</a>&#160;&#160;&#160;(1UL &lt;&lt; IFSR_FS1_Pos)</td></tr>
<tr class="memdesc:ga6fc93a02fbd1c968c70786a84428fca6"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: FS1 Mask.  <a href="#ga6fc93a02fbd1c968c70786a84428fca6">More...</a><br/></td></tr>
<tr class="separator:ga6fc93a02fbd1c968c70786a84428fca6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga487c29da2f2d648f149c4346f3093f72"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#ga487c29da2f2d648f149c4346f3093f72">IFSR_FS0_Pos</a>&#160;&#160;&#160;0U</td></tr>
<tr class="memdesc:ga487c29da2f2d648f149c4346f3093f72"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: FS0 Position.  <a href="#ga487c29da2f2d648f149c4346f3093f72">More...</a><br/></td></tr>
<tr class="separator:ga487c29da2f2d648f149c4346f3093f72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa17676ff0276b0fe93f92010fe35f6b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#gaa17676ff0276b0fe93f92010fe35f6b8">IFSR_FS0_Msk</a>&#160;&#160;&#160;(0xFUL &lt;&lt; IFSR_FS0_Pos)</td></tr>
<tr class="memdesc:gaa17676ff0276b0fe93f92010fe35f6b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: FS0 Mask.  <a href="#gaa17676ff0276b0fe93f92010fe35f6b8">More...</a><br/></td></tr>
<tr class="separator:gaa17676ff0276b0fe93f92010fe35f6b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga64ec6d573ec1efe1d6c36100ad1cd09d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#ga64ec6d573ec1efe1d6c36100ad1cd09d">IFSR_STATUS_Pos</a>&#160;&#160;&#160;0U</td></tr>
<tr class="memdesc:ga64ec6d573ec1efe1d6c36100ad1cd09d"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: STATUS Position.  <a href="#ga64ec6d573ec1efe1d6c36100ad1cd09d">More...</a><br/></td></tr>
<tr class="separator:ga64ec6d573ec1efe1d6c36100ad1cd09d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf74c1045a32a2d4de7ea6f0dbcf0d1b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#gaf74c1045a32a2d4de7ea6f0dbcf0d1b3">IFSR_STATUS_Msk</a>&#160;&#160;&#160;(0x3FUL &lt;&lt; IFSR_STATUS_Pos)</td></tr>
<tr class="memdesc:gaf74c1045a32a2d4de7ea6f0dbcf0d1b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">IFSR: STATUS Mask.  <a href="#gaf74c1045a32a2d4de7ea6f0dbcf0d1b3">More...</a><br/></td></tr>
<tr class="separator:gaf74c1045a32a2d4de7ea6f0dbcf0d1b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="gab0083a1d82b370a7e5208e39267bda22"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define IFSR_ExT_Msk&#160;&#160;&#160;(1UL &lt;&lt; IFSR_ExT_Pos)</td>
        </tr>
      </table>
</div><div class="memdoc">

</div>
</div>
<a class="anchor" id="gafb3d593ec56834b6a265744efd6340a8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define IFSR_ExT_Pos&#160;&#160;&#160;12U</td>
        </tr>
      </table>
</div><div class="memdoc">

</div>
</div>
<a class="anchor" id="gaa17676ff0276b0fe93f92010fe35f6b8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define IFSR_FS0_Msk&#160;&#160;&#160;(0xFUL &lt;&lt; IFSR_FS0_Pos)</td>
        </tr>
      </table>
</div><div class="memdoc">

</div>
</div>
<a class="anchor" id="ga487c29da2f2d648f149c4346f3093f72"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define IFSR_FS0_Pos&#160;&#160;&#160;0U</td>
        </tr>
      </table>
</div><div class="memdoc">

</div>
</div>
<a class="anchor" id="ga6fc93a02fbd1c968c70786a84428fca6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define IFSR_FS1_Msk&#160;&#160;&#160;(1UL &lt;&lt; IFSR_FS1_Pos)</td>
        </tr>
      </table>
</div><div class="memdoc">

</div>
</div>
<a class="anchor" id="ga9ecf4e123cfee3f0a19898a822fc0f62"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define IFSR_FS1_Pos&#160;&#160;&#160;10U</td>
        </tr>
      </table>
</div><div class="memdoc">

</div>
</div>
<a class="anchor" id="ga20639ca32a866d7b021e455b7a5d24c6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define IFSR_LPAE_Msk&#160;&#160;&#160;(0x1UL &lt;&lt; IFSR_LPAE_Pos)</td>
        </tr>
      </table>
</div><div class="memdoc">

</div>
</div>
<a class="anchor" id="gadfd49185eeb102fc69e0a0d28fd2c4a4"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define IFSR_LPAE_Pos&#160;&#160;&#160;9U</td>
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      </table>
</div><div class="memdoc">

</div>
</div>
<a class="anchor" id="gaf74c1045a32a2d4de7ea6f0dbcf0d1b3"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define IFSR_STATUS_Msk&#160;&#160;&#160;(0x3FUL &lt;&lt; IFSR_STATUS_Pos)</td>
        </tr>
      </table>
</div><div class="memdoc">

</div>
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<a class="anchor" id="ga64ec6d573ec1efe1d6c36100ad1cd09d"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define IFSR_STATUS_Pos&#160;&#160;&#160;0U</td>
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